The present invention relates to geographic positioning systems, in general, and to a method and geographic positioning receiver for acquiring signal code phases, in particular.
The Global Positioning System (GPS) is a satellite-based system developed by the United States (U.S.) Department of Defense to give accurate positional information to a GPS receiver anywhere in the world. A properly equipped GPS receiver may therefore be used in any setting in which position is desired and typically yields positional coordinates in three dimensions. The GPS system is enabled by a satellite orbital constellation made up of 24 or more satellites orbiting the earth in 12 hour orbits. The satellites are arranged in six orbital planes, each containing four satellites. The orbital planes are spaced sixty degrees apart and are inclined approximately fifty-five degrees from the equatorial plane. This constellation ensures that from four to twelve satellites will be visible at any time at any point on Earth.
The GPS satellites transmit data to be used by GPS receivers. The data includes satellite position data (ephemeris data) and satellite clock correction data. The GPS signal carrying the data includes a carrier signal that is bi-phase modulated with a 1,023 bit long Gold spreading code at a 1.023 MHz chip rate and that is repeated at 0.001 second intervals. The GPS signal is also modulated by data bits at a 50 bits per second (bps) rate and transmitted at a rate of twenty milliseconds per data bit. The 50 bps data includes information for determining a GPS-based time, or a clock time of the GPS satellite, and information for determining geographical location.
Detailed information on the data contained within the GPS signal is available in Interface Control Document ICD-GPS-200, revised in 1991, published by Rockwell International Corporation.
GPS receivers determine a position fix based upon the code phases of GPS signals received from GPS satellites. One specification of a GPS receiver is the time delay from when power is applied to the receiver to when the receiver acquires the satellite signal code phases, computes a position from these code phase measurements, and delivers position coordinates to the user. The time required to accomplish these steps is known as the time-to-first-fix (TTFF). GPS receivers with the shortest TTFF are preferred. The TTFF of any GPS receiver is determined by the individual receiver""s own unique hardware and software design.
In battery-powered, hand-held GPS receivers, the TTFF influences total battery life because the receivers must be powered on continuously while the user waits for position coordinates. A GPS receiver with a short TTFF consumes less total energy and has a longer battery life than a GPS receiver with a long TTFF. In addition, when a user is waiting for the first fix, a long TTFF can seem like an eternity.
Furthermore, a car having a GPS receiver may move and change location during a long TTFF. Thus, the position coordinates calculated after the TTFF may be inaccurate. The uncertainty in position may be particularly dangerous if the position coordinates are intended to be used in an emergency, such as in a system for identifying the location of an accident.
There have been many attempts to solve this problem in the past. All of these prior solutions attempt to decrease the signal search time by increasing the number of parallel search bins that can be tested simultaneously. For example, U.S. Pat. No. 5,600,670 (Turney) teaches the concept of speeding the search for a particular satellite by using multiple hardware channels. In order to search for a particular satellite in parallel, some channels are slaved to a main channel. The slave channels test successively delayed versions of a pseudo-noise (PN) code for the satellite, and each channel tests a particular PN code delay. Not all of the possible delays can be tested at once. Alternately, the Turney design can simply assign particular segments of the code phase or Doppler space to alternate channels so as to search the space in parallel.
As another example, U.S. Pat. No. 5,901,171 (Kohli) teaches the concept of time slicing the correlation process to implement a parallel correlator. In the Kohli design, only 22 half chip delays are tested per channel, and when combined with the 12 parallel channels, the design is capable of testing 264 possible code phase delays (assuming all 12 channels are used to search for the same channel). Kohli""s idea segments the 0.001 second repeating 1,023 chip long PN code into 11 chip segments, and each successive segment is then processed. It takes 186 total segments processed to equal one code repeat interval of 0.001 seconds. Furthermore, in the Kohli design, each segment, when stored, is applied to a number of channels. The channel processing for all channels occurs on one of the segments. The segment is then discarded and another segment is collected. Only 1 segment is kept while it is being processed.
As a further example, U.S. Pat. No. 6,009,118 (Tiemann) teaches the concept of a brute force parallel correlator. In this design, 2046 parallel correlators are used, and no time slicing of the signal processing occurs. In order to implement a 2046 state parallel correlator, much additional hardware is used.
Therefore, a need exists for an efficient method of acquiring signal code phases and a geographic positioning receiver that minimizes the TTFF, extends battery life, and provides more accuracy in determining position coordinates.
The present provides a geographic positioning receiver and a method of acquiring signal code phases in a geographic positioning receiver. A novel aspect of the present invention includes providing a geographic positioning receiver with: a memory with at least three portions, a correlator with an adder coupled thereto, and a comparator, a microprocessor, a mixer, and a numerically controlled oscillator coupled to each other and the memory. One step in acquiring signal code phases includes providing a predetermined pattern sequence receiving a first signal sequence. Another step includes storing the first signal sequence in a first memory portion and storing the predetermined pattern sequence in a second memory portion. Another step includes comparing the first signal sequence and the predetermined pattern sequence in the correlator. Another step includes generating correlation values. Another step includes adding the correlation values from the correlator into correlation sums in the adder. Another step includes storing the correlation sums from the adder in a third memory portion. Another step includes selecting by the comparator from the third memory portion a final correlation sum with a greatest magnitude from the correlation sums. Another step includes determining a code phase for the first signal sequence from the final correlation sum.